flip-flop circuit
英 [flɪp flɒp ˈsɜːkɪt]
美 [flɪp flɑːp ˈsɜːrkɪt]
触发电路
双语例句
- Design and Application of Hybrid SET-MOS Flip-flop Circuit
SET-MOS混合结构的触发器设计及应用 - Interlocked flip-flop and its application to multi-input asynchronous sequential circuit design
互锁触发器及其在设计多输入异步时序电路中的应用 - The Design of Arbitrary Value Flip-Flop Circuit and Register
任意值触发器电路与寄存器的设计 - The design principle of CMOS Master-Slave JD flip-flop is discussed, its circuit structure is presented, and its application example is given.
讨论了CMOS主从JD触发器的设计原理，提出了CMOS主从JD触发器的电路结构，并给出应用实例。 - Due to the introduction of the CPLD, the commutating logic circuit without circumfluence and the digital pulse flip-flop circuit represented to be more rapid, more flexible and good performance.
而无环流换向逻辑、数字脉冲触发器则因采用了CPLD，使得这两个环节反映出了速度快、灵活性高、性能好等特点。 - Flip-flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. In this thesis we place emphasis on the design of SCFL latches.
触发器是分接器的基本组成单元，建立时间和保持时间是影响电路速度的关键，所以减小建立时间和保持时间是触发器设计的主要目标，本文着重介绍了SCFL锁存器的设计和优化方法。 - Based on the analysis of the principle of digital logic analyzer circuit, this paper discusses the FPGA implementation method of its flip-flop circuit module and presents some programming of part circuits.
在分析数字逻辑分析仪触发电路工作原理的基础上，讨论了其触发电路模块的FPGA实现方法，给出了部分电路的程序设计。 - By using the ternary D-type flip-flop and the ternary set-state type flip-flop, this paper proposes the circuit designs of shift registers and ternary ring counters.
本文利用三值D型触发器和三值置态型触发器，提出了对三值移位寄存器和三值环形计数器的电路设计。 - The characteristics of the body contact devices show the existence of floating effect. SPICE simulation of the circuit indicates that body resistance has obvious influence on the speed of BC ( body contact) D flip-flop circuit.
SPICE模拟表明体串联电阻对体接触SOI数字D触发器速度特性有明显的影响。 - The phase frequency detector ( PFD) circuit is constituted with the dynamic D flip-flop ( DFF) and the delay circuit can, which can effectively overcome the dead area, and have high-speed and low power consumption features.
鉴频鉴相器电路采用动态D触发器（DFF）和延迟电路构成，能有效克服死区，具有高速和低功耗的特点。 - The D flip-flop loop-based approach adopts a loop circuit formed by multiple shift registers and inverters, generating multiple square-wave signals of equal time-delay/ initial phase differences, which are then reshaped to sine waves via low-pass filtering.
基于D触发器环路的相控阵信号发生技术采用多个移位寄存器和反相器构成的环路，生成多路延时／初始相位等差的方波信号，再经低通滤波整形为正弦波。